Some digital data streams, especially high speed serial data streams are sent without accompanying clock signals. The receiver generates a clock from an approximate frequency reference, and then phase-aligns to the transitions in the data using a clock and data receovery (“CDR”) process. Jitter in the signal, which is the undesired deviation from a true perodiocity of an assumed periodic signal, can cause data loss during the processing of the high speed data streams.
Jitter tolerant CDR circuits can be constructed using emitter coupled logic (“ECL”) with a tail source to provide amplitude and current stabilization. These circuits are often run at the 2.8-3.6V operating voltage that is typically used for high speed bi-polar logic. Reducing the voltage, which in turn reduces the power consumption, in these high speed data path circuits in a CDR or Serializer/Deserializer (“SerDes”) (such as data samplers, phase detectors, multiplexers, and demultiplexers) means performance is sacrificed.
The above-described deficiencies of high speed data path circuits operated at low voltage are merely intended to provide an overview of some problems of current technology, and are not intended to be exhaustive. Other problems with the state of the art, and corresponding benefits of some of the various non-limiting implementations described herein may become further apparent upon review of the following detailed description.